memory timing - microprocessor control signals and their sequence

The problems of address decoding in a microprocessor system are generally summarised in the question "where, when and how is the memory accessed?". Our first article on address decoding did not answer the "when" part of this question. For this reason we decided a second article was needed to deal with the timing of operations and signals. We also decided to have a look at an example of modifying an existing decoding system. memory timing elektor february 1984 memory timing A logic combination of most significant address lines can be used to provide an enable signal that is only active for certain configurations of the lines used. As we have already seen in our first article, this signal is applied to one or a number of memory ICs accessed by the least significant address lines, which, in fact, control the chip"s internal address decoder. Data is transferred via the data bus. No matter how high the clock frequency of the processor, the address and data signals do not appear either ...