I/O Extension Card For Ibm Pcs And Compatibles

50 triost19EXTENSION CARD FOR IBM PCs AND COMPATIBLES (Part 2) The concluding instalment deals mainly with the construction and testing of the I/O extension card, and also gives useful hints for programming. Table 4 shows how the logic level at the control input of the DAC selects between two ways of dividing the twelve bits be- tween two bytes (CTR1= 0: left justified data; CTRL =1: right justified data). Digital-to-analogueconversionisstarted whennewdataiswrittentotheleast ctrl=1 significant byte. Circuit description The circuit diagram of Fig. 7 is really quite straightforward because of its resemblance to the previously discussed block diagram (see Part 1). Bus buffer IC2 is an inverting type to save on ICs. Inverted address lines are applied to PAL (Programmable Array Logic) IC4, which is programmed to provide all chip select signals required on the card. Ports A and C in PPIs ICs and IC6 are wired to the I/O connector. Port B is used for generating control signals for a numb...