Single cycle mode for the Junior Computer - with logic level analyser

By connecting this auxiliary circuit, the Junior Computer can be run in single cycle mode. As opposed to single step operation, where a whole instruction is executed at a time, only a single clock cycle is processed in the single cycle mode. By combining the circuit with the logic analyser shown here, it is very easy to check the logic levels on the bus. The single cycle extension and the bus analyser help the operator trace hardware and software errors. The logic analyser is particularly handy for troubleshooting while the computer is "running". After a reset signal the CPU is in a defined condition. Depressing S1 causes single clocks to be generated, in which case the CPU will start to execute the reset cycle (8 clocks). After this, the two reset vectors, RESL (EFFC) and RESH (FFFD) will be applied to the address bus and it is at these addresses that the program starts. The "MCS 6500 Microcomputer Family Hardware Manual" (MOS Technology) contains further details about the execution o