Bridging the Gap Part II: Scaling Low-Cost SDRs via FPGA Gateware

In the first part of our series ( https://www.elektormagazine.de/labs/bridging-the-gap-with-smisdr-and-parliosdr ), we examined how the smiSDR (Raspberry Pi) and parlioSDR (ESP32-P4) projects are revolutionizing the ultra low cost SDR landscape. By cleverly utilizing network-based rf streams routed via Direct Memory Access (DMA) straight to parallel high-speed buses, the host processor could be almost completely offloaded. However, this pure "data pump" architecture reaches its physical limits at extreme bandwidths. Now, the community is demonstrating the next evolutionary step: the integration of a dedicated FPGA backbone.

If you want to feed a 14-bit DAC at, for example, 50 MSPS (Mega-Samples per Second), massive data streams are generated that push even Gigabit Ethernet and USB connections to the brink of stability. Furthermore, an architectural problem arises: A 16-bit wide high-speed bus (like the SMI or PARLIO), along with the necessary clock and control lines (SWE), occupies nearly all available GPIO pins of the host controllers. How can you control additional hardware parameters like NCO frequencies in such a system without having dedicated lines for SPI or I2C available?


The Solution: The FPGA Backbone and In-Band Signaling

Instead of wiring the host controller (Raspberry Pi or ESP32) directly to the DAC, the new gateware branch of the repositories introduces an intermediate layer. A low-cost FPGA is interfaced as a HAT or shield between the parallel bus and the RF front-end DAC.

To solve the issue of missing control pins, the FPGA implements in-band signaling. Control commands and raw baseband data share the exact same high-speed data bus. The state machine running inside the FPGA parses the incoming data stream in real-time, seamlessly separating configuration headers (commands for frequency shifts, phase adjustments, etc.) from the actual I/Q samples. Thus, the host can reconfigure the system "on-the-fly" without stalling the continuous data flow.

The protocol differentiates between raw I/Q data and command words purely based on Bit 15 and Bit 14.

The DSP Core: Hardware-Accelerated Digital Up Conversion (DUC)

The absolute centerpiece of this new architecture is hidden within the gateware/DUC module. A hardware-accelerated Digital Up Converter drastically alters the scalability of the system by offloading the signal processing from the host PC to the FPGA hardware.

Instead of forcing massive amounts of data across the network, the host (e.g., via GNU Radio) now merely streams an extremely narrow, resource-efficient baseband signal (e.g., 250 ksps to 1.25 MSPS). Inside the FPGA, this signal then passes through the DUC pipeline:

With the implementation of the FPGA gateware and the DUC pipeline, the show goes on. What began as an elegant hack to replace obsolete USB-to-VGA adapters has matured into a professional SDR architecture.

For applications like the COHIRADIAStreamer, which reconstructs historical broadcast signals, this is a game-changer: I/Q data can be stored with extreme space efficiency and streamed over basic networks, while the low-cost FPGA handles the heavy DSP lifting of frequency mixing.


Future Horizons: DDC, ESP32-S31, and the "FPGA-Only" Vision

While the implementation of the hardware DUC has revolutionized the transmission (TX) pipeline, development is not standing still. The radiolab81 community and the maintainers behind the smiSDR and parlioSDR projects are already targeting the next milestones that aim to elevate this low-cost SDR ecosystem into the professional tier.

The Logical Progression: Digital Down Conversion (DDC) Currently, the focus is heavily weighted toward the transmission side. However, the DMA-driven buses (SMI and PARLIO) are inherently bidirectional. The next major leap in development is the implementation of Digital Down Conversion (DDC) within the FPGA.

This is the exact mirror image of the DUC: A high-speed Analog-to-Digital Converter (ADC) captures the full RF spectrum (e.g., at 50 MSPS). This massive data stream flows directly into the FPGA. There, the signal is down-converted via a digital mixer (NCO) and reduced to a narrowband I/Q stream through decimation filters (the counterparts to the interpolation filters). Only this resource-efficient baseband stream is then sent via the parallel bus to the host processor and subsequently across the network. This expansion transforms the pure transmitters into fully functional, network-attached full-duplex transceivers (RX/TX).

The Software Bridge: Native GNU Radio OOT Modules The most capable hardware only unleashes its full potential through seamless software integration. While in-band signaling—the multiplexing of control commands and I/Q data on the same bus—revolutionizes the hardware architecture, it presents a hurdle on the host PC side. Currently, these combined data streams require custom scripts or raw network pipes to be properly multiplexed.

Therefore, the logical progression for the project's roadmap is the development of dedicated GNU Radio Out-of-Tree (OOT) blocks (a gr-ibs_encoder/decoder module). Such a GNU Radio component would completely abstract the process: it would provide a standard input for the complex baseband stream and a separate asynchronous message port for control commands like frequency or gain adjustments. The OOT block would internally handle the encoding of headers, multiplex the payload, and stream the finalized in-band packet directly to the microcontroller via TCP/UDP. 

Hardware Evolution: Espressif’s ESP32-S31 On the microcontroller front, the ESP32-S31 is poised to be a game-changer. As analyzed in the first part of this series, the ESP32-P4 currently suffers from an Ethernet bottleneck, often necessitating USB workarounds to achieve higher baseband rates.

The new ESP32-S31, however, brings native Gigabit Ethernet capabilities to the table. In combination with the PARLIO interface, this chip will propel the parlioSDR architecture to the performance level of a Raspberry Pi 4—but at a fraction of the cost, power consumption, and physical footprint. 

The Final Stage: The "FPGA-Only" Vision Parallel to these SBC and MCU-based approaches, another radical vision is emerging within the radiolab81 community: the elimination of the host processor as a middleman.

In an "FPGA-Only" version, the network stack would be integrated directly into the FPGA. By utilizing resource-efficient soft-core processors  or dedicated hardware MAC blocks within the FPGA fabric, TCP/UDP streams could be received and processed without the detour through a Raspberry Pi or ESP32. The chain would be reduced to: Network → FPGA (with integrated DDC/DUC) → ADC/DAC.