Euclidean Sequencer Without Microcontroller
This CMOS circuit produces Euclidean patterns and CV sequences using nothing more than counters, logic gates, and clever timing.
Click here for an analog Voltage-Controlled Euclidean Rhythm Generator VC-ERG as 3U Eurorack module
In music, a Euclidean rhythm is a way of distributing a number of beats as evenly as possible over a sequence of steps. It spreads K pulses over N steps (where K and N are integers) so that the pulses are as evenly spaced as possible. As an example, let’s say N = 8 steps and K = 3 pulses. A Euclidean rhythm gives 1 0 0 1 0 0 1 0 instead of clustering the pulses like 1 1 1 0 0 0 0 0 or some other uneven distribution (e.g. 1 0 1 0 1 0 0 0). Euclidean rhythm generators and sequencers are popular in modular music synthesizers.
The circuit presented here generates Euclidean-spaced trigger pulses entirely with discrete CMOS logic; it does not need a microcontroller to do the maths. The circuit outputs trigger pulses (for drums, envelopes, etc.) and has an 8-step control-voltage (CV) output triggered by these pulses. The main clock signal is available for synchronizing other modules and devices to the sequencer. The other way around is possible too, meaning that the sequencer itself can be triggered from an external source. A reset input has been provided to allow starting a sequence at the beginning. Inputs and outputs are implemented as T(R)S connectors.
The circuit around Schmitt-trigger NAND gate IC1B, wired as inverter, implements a simple pulse generator. Potentiometer P1 controls the pulse rate, while resistor R1 defines the pulse width. With the given values, the rate is adjustable from approximately 0.4 Hz to 23 Hz. The pulse width is 15 ms. It works as follows.
IC1B is a Schmitt-trigger inverter. Such a device has hysteresis, meaning that it switches at different input voltages depending on whether the signal is rising or falling.
When the output of IC1B is high, capacitor C2 is charged through R1 and D1. When the rising trigger level of the gate is reached, the output switches low and C2 can discharge through D2, R18 and P1. When the voltage on C2 decreases below the falling trigger threshold, the output of the gate switches back to high. As a result, the durations of the high and low parts of the clock signal can be set individually. Together, they control the frequency.
IC1C together with C3, R2 and P2 forms a gated square wave oscillator. When pin 8 of IC1C is logic high, the circuit oscillates; when pin 8 is logic low, the oscillator is blocked and its output remains high. P2 allows adjusting the frequency of this oscillator between about 200 Hz and 2 kHz with the given component values.
The output of oscillator IC1C is fed into binary counter IC2. If IC1C would be a free-running oscillator, IC2 would simply divide its output frequency by 32 (output Q4) in a very regular and rather uninteresting way. However, by gating IC1C, the number of pulses entering the counter can be controlled and it will no longer overflow as regularly as before because it becomes synchronised to the gate rate, which is the output of pulse generator IC1B.
As an example, assume that each gate pulse causes IC1C to generate 9 pulses. In other words, for every gate pulse, counter IC2 advances by 9 steps. After three gate pulses, the count reaches 27. The fourth gate pulse adds another 9 pulses, bringing the count to 36. Output Q4 of IC2 overflows at a count of 32. Although the counter continues counting to 36 (which is 100100 in binary), Q4 only depends on bits 0 to 4. Bit 5 is therefore ignored, so the effective count can be considered as 36 – 32 = 4.
The next overflow of Q4 will occur when another 32 counts have been accumulated. Since we are adding 9 counts per gate pulse, this happens during gate pulse number 8, the fourth pulse after the first overflow, leaving a remainder of 8.
Continuing in this way, Q4 overflows during gate pulses 11, 15, 18, 22, 25, and 29. On gate pulse nr. 32, the remainder returns to 0, and the sequence repeats. The resulting sequence or rhythm therefore is 10001000 10010001 00100010 01000100.
In the case of 10 pulses per gate the rhythm will be 10001001 00100100, a sequence that repeats after 16 steps. All sequences with an even number of pulses per gate repeat after 16 steps. Attached below is a graph showing the timing diagrams for the first 16 cases.
The signal on output Q4 is an almost perfect square wave. It is differentiated by C1 and R3 and shaped and inverted by IC1A to create clean trigger pulses on the output K1. D3 provides overvoltage protection for IC1A.
Now that we understand the circuit, let’s discuss some interesting details.
When the gate is short, oscillator IC1C must be fast to allow enough pulses going through. In this case, output Q4 will toggle tightly in phase with the gate (“on the beat”). When the gate is long, oscillator IC1C must be slow to avoid Q4 to toggle multiple times per gate. (The pulse shaper around IC1A filters out fast multiple toggles, but the sequencer will run wild.) Now, the coupling between Q4 and the gate is less tight, and some “swing” is introduced.
Swing makes the machine more human, and the amount can be controlled by R1 (add a potentiometer in series). Increasing its value makes the gate longer. It should not be decreased much, as this will stop the pulse generator. The rate of the pulse generator is determined by both R1 and P1 (limited by R18), so adjusting swing also changes the tempo slightly.
Because IC1C is far from being a precision oscillator and, what’s more, controlled by a coarse potentiometer, it is possible that in certain settings the number of pulses per gate is not always the same. There may be one more or less. This will result in the sequence slowly shifting, adding a nice random touch to it.
A reset input has been provided too, so sequences can be started or reset on (remote) controlled moments. Note, however, that the sequencer does not produce a trigger on the very first beat (right after pressing reset).
All in- and outputs are protected by current-limiting resistors.
LED1 flashes briefly for each generated trigger pulse.
Click here for an analog Voltage-Controlled Euclidean Rhythm Generator VC-ERG as 3U Eurorack module
240583-01
In music, a Euclidean rhythm is a way of distributing a number of beats as evenly as possible over a sequence of steps. It spreads K pulses over N steps (where K and N are integers) so that the pulses are as evenly spaced as possible. As an example, let’s say N = 8 steps and K = 3 pulses. A Euclidean rhythm gives 1 0 0 1 0 0 1 0 instead of clustering the pulses like 1 1 1 0 0 0 0 0 or some other uneven distribution (e.g. 1 0 1 0 1 0 0 0). Euclidean rhythm generators and sequencers are popular in modular music synthesizers.
The circuit presented here generates Euclidean-spaced trigger pulses entirely with discrete CMOS logic; it does not need a microcontroller to do the maths. The circuit outputs trigger pulses (for drums, envelopes, etc.) and has an 8-step control-voltage (CV) output triggered by these pulses. The main clock signal is available for synchronizing other modules and devices to the sequencer. The other way around is possible too, meaning that the sequencer itself can be triggered from an external source. A reset input has been provided to allow starting a sequence at the beginning. Inputs and outputs are implemented as T(R)S connectors.
The Circuit in Detail
Refer to the schematic of the Euclidean Sequencer attached below .The circuit around Schmitt-trigger NAND gate IC1B, wired as inverter, implements a simple pulse generator. Potentiometer P1 controls the pulse rate, while resistor R1 defines the pulse width. With the given values, the rate is adjustable from approximately 0.4 Hz to 23 Hz. The pulse width is 15 ms. It works as follows.
IC1B is a Schmitt-trigger inverter. Such a device has hysteresis, meaning that it switches at different input voltages depending on whether the signal is rising or falling.
When the output of IC1B is high, capacitor C2 is charged through R1 and D1. When the rising trigger level of the gate is reached, the output switches low and C2 can discharge through D2, R18 and P1. When the voltage on C2 decreases below the falling trigger threshold, the output of the gate switches back to high. As a result, the durations of the high and low parts of the clock signal can be set individually. Together, they control the frequency.
IC1C together with C3, R2 and P2 forms a gated square wave oscillator. When pin 8 of IC1C is logic high, the circuit oscillates; when pin 8 is logic low, the oscillator is blocked and its output remains high. P2 allows adjusting the frequency of this oscillator between about 200 Hz and 2 kHz with the given component values.
The output of oscillator IC1C is fed into binary counter IC2. If IC1C would be a free-running oscillator, IC2 would simply divide its output frequency by 32 (output Q4) in a very regular and rather uninteresting way. However, by gating IC1C, the number of pulses entering the counter can be controlled and it will no longer overflow as regularly as before because it becomes synchronised to the gate rate, which is the output of pulse generator IC1B.
As an example, assume that each gate pulse causes IC1C to generate 9 pulses. In other words, for every gate pulse, counter IC2 advances by 9 steps. After three gate pulses, the count reaches 27. The fourth gate pulse adds another 9 pulses, bringing the count to 36. Output Q4 of IC2 overflows at a count of 32. Although the counter continues counting to 36 (which is 100100 in binary), Q4 only depends on bits 0 to 4. Bit 5 is therefore ignored, so the effective count can be considered as 36 – 32 = 4.
The next overflow of Q4 will occur when another 32 counts have been accumulated. Since we are adding 9 counts per gate pulse, this happens during gate pulse number 8, the fourth pulse after the first overflow, leaving a remainder of 8.
Continuing in this way, Q4 overflows during gate pulses 11, 15, 18, 22, 25, and 29. On gate pulse nr. 32, the remainder returns to 0, and the sequence repeats. The resulting sequence or rhythm therefore is 10001000 10010001 00100010 01000100.
In the case of 10 pulses per gate the rhythm will be 10001001 00100100, a sequence that repeats after 16 steps. All sequences with an even number of pulses per gate repeat after 16 steps. Attached below is a graph showing the timing diagrams for the first 16 cases.
A Discrete Phase Accumulator
The process described above is known as phase accumulation, and the circuit can therefore be considered a phase accumulator. Phase accumulation is a common technique for generating arbitrary frequencies in for instance software. Readers familiar with drawing lines on two-dimensional pixel displays may recognize Bresenham’s line algorithm.The signal on output Q4 is an almost perfect square wave. It is differentiated by C1 and R3 and shaped and inverted by IC1A to create clean trigger pulses on the output K1. D3 provides overvoltage protection for IC1A.
Add a Sequencer
Because IC2 is a 12-bit counter we can use some of the remaining outputs to drive analog multiplexer IC3. If we think of outputs Q5, Q6 and Q7 as a 3-bit counter clocked by Q4, then it will become clear that the multiplexer moves to its next position on every tick on Q4. The voltage of each step on the output of IC3 (on K3) can be adjusted with a potentiometer (P3 to P10). When VCC is 12 V, the CV output will be in the range of 0 V to 10 V.Now that we understand the circuit, let’s discuss some interesting details.
Add Swing
As explained, the length of the gate pulse determines how many pulses enter the counter for each gate pulse. Here hides a compromise.When the gate is short, oscillator IC1C must be fast to allow enough pulses going through. In this case, output Q4 will toggle tightly in phase with the gate (“on the beat”). When the gate is long, oscillator IC1C must be slow to avoid Q4 to toggle multiple times per gate. (The pulse shaper around IC1A filters out fast multiple toggles, but the sequencer will run wild.) Now, the coupling between Q4 and the gate is less tight, and some “swing” is introduced.
Swing makes the machine more human, and the amount can be controlled by R1 (add a potentiometer in series). Increasing its value makes the gate longer. It should not be decreased much, as this will stop the pulse generator. The rate of the pulse generator is determined by both R1 and P1 (limited by R18), so adjusting swing also changes the tempo slightly.
Because IC1C is far from being a precision oscillator and, what’s more, controlled by a coarse potentiometer, it is possible that in certain settings the number of pulses per gate is not always the same. There may be one more or less. This will result in the sequence slowly shifting, adding a nice random touch to it.
More Channels
Because only one Euclidean channel is a bit meagre, the gate pulse is also routed to connector K2 so that it can be used to clock other sequencers. This is possible thanks to Stop/Run switch S2, because, when set to Stop, K2 can be used as a gate input. For this reason, the output pulse on K1 is shaped to have a pulse width similar to the gate pulse, thus allowing multiple sequencers to be connected in series or in parallel. Similarly, when using an external clock signal, use pulses with a duration of about 15 ms.A reset input has been provided too, so sequences can be started or reset on (remote) controlled moments. Note, however, that the sequencer does not produce a trigger on the very first beat (right after pressing reset).
All in- and outputs are protected by current-limiting resistors.
LED1 flashes briefly for each generated trigger pulse.
Power Supply
One of the reasons to opt for CMOS logic in this circuit is its wide power supply range. Connector K4 conforms to the 16-way power connector standard of modular synthesizers that usually run from +/-12 V. Only +12 V is needed here, but the circuit will also work with a +5 V supply (doing so will limit the CV level to about 4 V) or a 9-volt battery. The current consumption is less than 10 mA.Click here for an analog Voltage-Controlled Euclidean Rhythm Generator VC-ERG as 3U Eurorack module
240583-01
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