A Euclidean Rhythm Generator (ERG) distributes a chosen number of beats as evenly as possible across a fixed number of steps. It is a simple and effective way to create rhythms that sound natural and musical. Many traditional rhythms from around the world can be generated using this technique.
 
Euclidean rhythm generators are popular in modular synthesizers, but most rely on digital algorithms. This project takes a different approach by generating Euclidean rhythms entirely in analog hardware using voltage-controlled phase accumulators. The result is a unique three-channel Eurorack module whose beat density can be controlled with CV signals, the VC-ERG.
 
The Euclidean rhythm generator described here differs from most similar devices in several important ways:

• It does not use the Euclidean algorithm.
• It does not have a step parameter.
• The beat density is voltage-controlled.
• It has three channels instead of only one.
• It is fully analog.

Voltage-Controlled Beat Density

Voltage-controlled in this project applies to the beat density. There is no step counter but only an adjustable clock generator. If we call the number of beats within a certain amount of clock cycles the beat density, then this density can be set with a voltage. The control voltage (in the range from 0 V to 10 V) can come from an external source like a low-frequency oscillator or an envelope generator, but it can also be a simple potentiometer as the one included on the board.
 
The internal clock generator is not voltage-controlled, but an external clock signal (10 V) can be used instead, for example a pulse signal from a voltage-controlled oscillator (VCO). This not only adds voltage control over the rhythm rate, but also allows the VC-ERG to be synchronized with other equipment.
 
The VC-ERG features three almost identical channels driven by the same clock, so they remain synchronized. One channel is useful, two are better, but three make it possible to create much more interesting patterns. Of course, you do not have to use all three at the same time.

Phase Accumulators Instead of Steps

This leaves the final major difference: the VC-ERG does not use the Euclidean algorithm to derive its rhythms. Instead, it uses phase accumulators. A detailed explanation is given at the end of this page in the section Why Phase Accumulators Produce Euclidean Rhythms. For more information about phase accumulators and a digital implementation without microcontroller, see my article in the Circuit Special 2026 or on Elektor Labs.
 
The phase accumulator used in the VC-ERG produces a beat each time it overflows. By making the phase increment proportional to a control voltage, the circuit becomes a voltage-controlled phase accumulator capable of producing voltage-controlled rhythms. In practice, the VC-ERG behaves as a voltage-controlled frequency divider, which explains why the control potentiometers are labelled “DIV” on the front panel.

The Circuit

After this introduction, let us move on to the circuit. The design files and other resources for this project can be found at the bottom of this page.
 
The block diagram is attached below. A variable clock generator provides the common timing signal for the three channels. Its square-wave output is first passed through a differentiator before being distributed to the three channels. With the help of a control voltage (CVx), the differentiated clock signal is transformed into a pulse-width-modulated (PWM) signal. The pulse width determines the amount added to the phase accumulator on each clock pulse. When the accumulator reaches its limit, it generates an event that is converted by the pulse shaper into a clean trigger pulse, producing Out1, Out2 or Out3. Switching at the outputs allows the middle channel to be combined with either the upper or lower channel, providing additional rhythmic patterns at Out1 or Out3. In addition, the phase-accumulator voltage of either Channel 2 or Channel 3 is made available as a CV output.
 
The schematic (see download section) simply fills in the blocks. For clarity, it has been divided into two parts: one showing the circuitry shared by all three channels (main), and another showing a single channel (channel1). We will start with the global circuitry.

Global Clock and Control Circuitry

A basic square-wave oscillator is built around IC1D. As this is a classic design, I will not explain its operation here. Its frequency is adjusted with P1, while switch S4 selects the range. The frequency range is from 0.75 Hz to 20 Hz (low) and from 1.5 Hz up to approx. 40 Hz (high). Switch S2 is the Run/Stop control. The clock signal is routed to three destinations: LED1, through pulse-shaping components C1, R2, and T1, to indicate the clock rate; connector K2, where it can clock other circuits or accept an external clock when S2 is in the Stop position; and C4, from where it is fed to the three almost identical phase-accumulator channels.
 
D19 and D20 are 12-V TVS diodes that protect input/output K2 and output K1 against voltage spikes that may occur when patch cables carrying signals are plugged in or removed.
 
IC1B together with R12, R13 and C7 provides a virtual ground so that all the other op-amps can be powered from an asymmetric supply of 12 VDC. A symmetric supply would have allowed to simplify the circuit somewhat, but an asymmetric supply improves its flexibility.
 
IC1C is unused and wired for doing nothing.
 
To the right of the three channel blocks is buffer amplifier IC1A. It provides a control-voltage output on K1 based on the phase-accumulator voltage of either Channel 2 or Channel 3. This voltage rises at the clock rate and resets at every beat. It can, for example, be used to control a voltage-controlled filter (VCF). When C3 is a 0-ohm resistor, the output will be between 0 V and 10 V. Mount a 10 µF capacitor instead if you want to remove the DC part and center it around 0 V.
 
Connector K3 is the power supply connector compatible with the common 16-pin power distribution standard found in many modular synthesizer systems. Only +12 V and GND are needed so it may be replaced with a smaller 10-pin header (also common) or something else. D1 provides reverse-polarity protection and C5 adds some filtering.

Inside a Rhythm Channel

The ERG core is identical for all three channels except for diode D8, which is only present in Channel 2. We might as well get this detail out of the way right now. D8 connects to S1 in the global-circuitry schematic that routes it to either Channel 1, Channel 3 or nowhere. In other words, the output of Channel 2 can optionally be added to the output of Channel 1 or Channel 3.
 
Back to the schematic of the ERG channel. The global clock signal is applied to the non-inverting input of IC2C, configured as a comparator. Its output produces clock pulses that charge capacitor C9 through D3 and R19. The wider these pulses, the more charge is transferred to C9 and the faster its voltage rises.
 
The voltage across C9 is monitored by IC2B, another comparator but with hysteresis provided by R22 and R23. As soon as the voltage on C9 exceeds the reference voltage at the non-inverting input of IC2B, its output switches low. This rapidly discharges C9 through D2 and R16, after which the output immediately returns high.
 
Because C9 can only charge while a clock pulse is present, this discharge-and-reset action occurs during the clock pulse. The discharge path is much faster than the charging path, so C9 is almost instantly emptied. If the clock pulse has not yet ended, the remaining part of the pulse immediately starts charging C9 again. The voltage reached before the pulse ends is retained until the next clock pulse arrives. In other words, the unused part of the charging pulse becomes the remainder that is carried over to the next cycle, exactly as in a phase accumulator. See the attached phase accumulator graph for details.
 
The output of IC2B passes through diode D4 to the inverting pulse stretcher IC2A. The resulting pulse is long enough to flash LED2 and trigger an envelope generator or another circuit requiring a trigger signal. The pulse duration is determined by C8 and R17.
 
In the case of Channel 2, the output of IC2B is also passed through D8. If S1 of the global circuitry is set to its top position, the signal arrives at the anode of D4, the trigger input of Channel 1.
 
Like D19 and D20, D13, D14 are 12-V TVS diodes. They protect the inputs and outputs of the VC-ERG against voltage spikes that may occur when patch cables carrying signals are plugged in or removed.
 
The potentiometer and resistors around IC2D provide both a control-voltage input at K4, whose level is adjusted by P2, and a manual beat-density control, P3. IC2D sums these voltages and applies the result to the inverting input of comparator IC2C.

Voltage-Controlled Rhythm

This brings us to the heart of the design: voltage-controlled rhythm.
 
The pulse rate at the output of IC2B depends on how quickly capacitor C9 charges. The charging current is supplied by the pulses produced by IC2C. Short pulses transfer less charge than long ones, causing C9 to charge more slowly. Consequently, the oscillation frequency is determined by the width of the pulses generated by IC2C. This is where C4 and R9 in the global circuitry (Figure 2) become important.
 
Together, C4 and R9 form a differentiator that converts the global clock signal into narrow pulses with a gradually decaying trailing edge. A comparator monitors this falling edge and switches when it crosses an adjustable reference voltage. Raising the reference voltage shortens the output pulse, while lowering it lengthens the pulse. The result is a voltage-controlled pulse-width modulator (PWM), whose output pulse width determines the charging rate of C9 and, ultimately, the rhythm generated by IC2B. See also the attached PWM graph.
 
Diode D12 and R10 remove the negative-going pulses due to the falling edges of the clock signal that may disturb IC2C. As this is a TL084, it exhibits phase reversal when its input common-mode voltage exceeds the specified range (i.e., goes below something like 1.5 V in this circuit). Instead of simply saturating, the output switches to the opposite polarity, something we don’t want. D12/R10 mitigate this issue.

Mechanical Design

The complete circuit fits on a double-sided printed circuit board (PCB) of dimensions of approx. 112 mm by 56 mm. In Eurorack units, this corresponds to a width of 11 HP. This is not very large and necessitates small knobs, but the objective was to limit the required amount of rack space. The height allows fitting the board between the mounting bars of a standard 3U rack.
 
The mainboard is accompanied by a front-panel board of dimensions 3U (128.5 mm) by 11 HP (55.76 mm). The front panel attaches to the 3.5-mm jack sockets mounted on the top side of the main board.

Assembling the Board

The PCB has components on both sides. All through-hole components, except the power connector K3, are mounted on the top side, while all SMD components, together with K3, are mounted on the bottom side. A practical assembly sequence is to solder the SMD components first, followed by the through-hole parts.
 
If, like me, you prefer not to solder the SMD components yourself, consider using PCBWay’s PCB assembly service. Besides saving you the time and effort of sourcing the components, the professionally assembled board will almost certainly look better than one assembled by hand. You might even try ordering a fully assembled board at PCBWay.
 
Insert the 3.5-mm jack sockets into the board, place the front panel over them, and secure them with the supplied round nuts. Carefully turn the board assembly over and solder the sockets to the mainboard. Using the front panel as an alignment jig ensures that the sockets remain straight.
 
Remove the front panel and insert the LEDs in the mainboard, observing their polarity. Refit the front panel and guide the LEDs through their corresponding holes. Turn the assembly over once more and solder the LEDs to the board.
 
Repeat this procedure for the toggle switches. Refitting the front panel is easiest when all switches point in the same direction. The switches can move while the assembly is being handled, so take care to align and solder them neatly and squarely to the mainboard. Note that S1 is a three-position toggle switch with a centre position (ON-OFF-ON).
 
Remove the front panel once more and solder the potentiometers to the mainboard. Suitable potentiometers are 25 mm high, measured from the top side of the PCB. It is important that enough shaft sticks out of the front panel to allow plugging knobs on them. And now that we’re on the subject of knobs, here is an important detail: when using the potentiometers from the component list, you’ll need so-called 180-degree knobs for D-type shafts. Zero, 90, or 270-degree knobs will fit but the rotation indicator will be wrong. Of course, you can use knobs without rotation indicator, but that’s less practical. Another option is to use potentiometers with knurled (teethed) shafts. Suitable knobs can be found online.
 
Finally, solder the power connector to the bottom side of the mainboard.

Grounding the Front Panel

The final assembly step is to establish an electrical connection between the PCB ground and the front panel. Because the 3.5-mm jack sockets have plastic bodies, they do not provide a conductive path between the PCB and the ground plane of the front panel. If your Eurorack case already connects the front panel to the system 0 V, or if you prefer to keep the panel electrically isolated, you can skip this step.
 
Otherwise, attach a solder lug to either K1 or K5. I used a solder lug with an 8.2-mm inner diameter. Connect the lug to the nearest GND test point with a short piece of wire. Refit the front panel for the last time and secure it to all sockets, making sure to tighten the socket carrying the solder lug firmly to ensure a reliable electrical connection.
 
Press the knobs onto the potentiometer shafts, and your Voltage-Controlled Euclidean Rhythm Generator is ready to groove!

Specifications

Fully analog Euclidean rhythm generator with voltage-controlled beat density

• Independent rhythm channels 3
• CV output 1
• Clock rate Lo: 0.8...20 Hz; Hi: 1.7...40 Hz
• Trigger output level 10 V
• CV output level max 10 V
• CV input range 0...10 V
• Clock input level 10...12 V
• Supply voltage 12 V
• Current consumption 25 mA

 

Why Phase Accumulators Produce Euclidean Rhythms

A phase accumulator may seem like a clever circuit trick, while a Euclidean rhythm generator sounds like a purely mathematical construct. In reality, the two are closely related. Both solve exactly the same problem: distributing a fixed number of events as evenly as possible over a fixed number of time steps.

Suppose we want to distribute k beats over n clock steps. A digital phase accumulator does this using only addition, subtraction and a comparison:
 
The important detail is that the remainder is not discarded. It carries the fractional remainder from one step to the next, allowing it to be taken into account on subsequent clock steps. This is what spreads the beats evenly.

From Line Drawing to Rhythm Generation

Now consider drawing a straight line on a pixel display. Suppose the line advances n pixels horizontally and k pixels vertically. At each horizontal pixel position, the drawing algorithm must decide whether to move up by one pixel. A digital differential analyser (DDA) does this by accumulating the fractional vertical displacement. Whenever the accumulated fraction reaches one pixel, the line steps upward.

This is exactly what the phase accumulator does. Replace vertical pixel by beat and horizontal pixel by clock step and the algorithms become identical.

A classical DDA uses floating-point arithmetic. Bresenham’s line algorithm is an integer version of the same idea that requires only additions, subtractions and comparisons. It was developed at a time when floating-point arithmetic was too slow and expensive for real-time graphics. In essence, Bresenham’s algorithm is an integer DDA, and therefore mathematically equivalent to the phase accumulator used in the VC-ERG presented in this article.

Harris and Reingold show that Bresenham’s line algorithm can be viewed as an implementation of Euclid’s algorithm. Since a phase accumulator performs the same error accumulation as Bresenham’s algorithm, it generates the same maximally even distributions.

Euclid’s algorithm constructs a maximally even pattern by repeatedly dividing and distributing the remainder. A phase accumulator reaches the same result incrementally by preserving the remainder from one clock step to the next. One algorithm works by repeated division, the other by repeated addition, but both exploit the same mathematical principle.

Thus, the most precise conclusion is:

A normalized phase accumulator whose phase ranges from 0 to 1, using a phase increment of k/n, produces a beat whenever the phase wraps around from 1 back to 0. It therefore provides an elegant hardware implementation of Euclidean rhythm generation. No divider is required, no recursive algorithm is executed, and — at least in the VC-ERG — no software is involved.

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