FPGA Partitioning Tool Boosts Prototype Performance

December 10, 2013 | 14:37
FPGA Partitioning Tool Boosts Prototype Performance
FPGA Partitioning Tool Boosts Prototype Performance

Wasga Compiler from Flexras Technologies is a multi-FPGA partitioning tool for ASIC designers who use FPGA-based systems to verify their designs and validate software integration. It automatically partitions large designs into multiple FPGAs while meeting constraints on chip resources, connectivity and clock frequencies.

 

The compiler maps Register Transfer Level (RTL) and/or gate-level designs onto multi-FPGA platforms. The inputs are the design, the board description, the timing constraints and optional partitioning constraints. The outputs are the bitstreams for FPGAs and reports. The flow is fully automatic and can be semi-automatic if the user wants to run it in step mode. Advanced automatic partitioning algorithms search for the best partition with the fewest inter-FPGA connections and the highest system performance. All user constraints and directions, including manual grouping, target system interface and FPGA filling rate, are considered.

 

The tool features a graphical user interface to simplify project setup. It supports automatic and/or manual placement and routing and integrates very high speed multiplexing IPs to increase inter-FPGA bandwidth. It also supports SDC for timing constraints and budgeting, provides system level static timing analysis, drives and runs FPGA back-end flows, meets clock frequency requirements for running software, and facilitates iterative runs and verification.

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