Cypress has unveiled the PSoC 4 programmable system-on-chip architecture, which combines analog and digital fabric and capacitive touch technology with ARM’s power-efficient Cortex-M0 core. The truly scalable, cost-efficient architecture delivers flexibility, analog performance and integration, along with access to dozens of free PSoC Components — “virtual chips” in Cypress’s PSoC Creator integrated design environment. The new device class will challenge proprietary 8-bit and 16-bit microcontrollers (MCUs), along with other 32-bit devices. Cypress plans to announce the availability of new PSoC 4 families in the first half of 2013.
The PSoC 4 architecture keeps power leakage to 150 nA while retaining SRAM memory, programmable logic, and the ability to wake up from an interrupt. In stop mode, it consumes only 20 nA while maintaining wake-up capability. It has the widest operating voltage range of any Cortex-M0-based device, enabling full analog and digital operation from 1.71V to 5.5V. The architecture facilitates integrated, high-performance custom signal chains and provides both configurable analog and flexible routing.
PSoC solutions bring the flash-based equivalent of a field-programmable ASIC to embedded designs without lead-time or NRE penalties. PSoC integrates configurable analog and digital circuits with an on-chip microcontroller, reducing component count and simplifying revisions. A single PSoC device can integrate as many as 100 peripheral functions, accelerating cycle time and improving quality while reducing board space, power consumption, and system cost.