The D68000 IP core from Digital Core Design emulates the classic Motorola M68000 16/32-bit microprocessors. Fully compatible with the original M68k family of processors but featuring an improved architecture and an enhanced instruction set for better performance, the D68000 can be implemented on FPGAs from Altera, Lattice or Xilinx, as well as ASIC and SoC devices.
The core is binary-compatible with the m68k family of microprocessors. It has a 16-bit data bus and a 24-bit address bus and can address 4 GB of memory. Code is compatible with the MC68008 and upward compatible with the MC68010 virtual extensions and the MC68020 32-bit architecture. MULS and MULU instructions, as well as their DIVS and DIVU counterparts, take just 28 clock cycles. Optimised shifts and rotations, combined with shorter effective address calculation time and the elimination of idle cycles, make the new core much more efficient than the original Motorola architecture.
The D68000 is able to run the uCLinux operating system, making it suitable for use as an HTTP server or an FTP client. The D68000 comes with an automated test bench and a complete set of tests for easy package validation at every stage of the design flow. It is also compatible with the DCD BDM hardware debugger, which provides debugging capability not only for the IP core but also for the entire device.