According to the press release Lattice see the ECP5 family’s architecture useful as a companion chip to an ASIC or ASSP where it can perform critical functions and deliver best value below 100k LUTs. Lattice anticipates that this approach gives a more flexible overall design solution with the major functionality implemented in an ASIC or ASSP while an ECP5 chip takes care of future, evolving features of the design.
The ECP5 family is the only FPGA portfolio that enables 85k LUTs and SerDes in a 10mm x 10mm package, amounting to twice the functional density of competing solutions. Smart ball depopulation simplifies package integration with existing PCB technology and reduces overall system cost. Enhancements leading to 30% lower total power than other FPGA solutions include stand-by mode operation of individual blocks including SerDes, dynamic IO bank controllers and operation at reduced voltage. This enables single channel 3.25 Gpbs SerDes functions starting below 0.25 W and quad channel SerDes functions starting below 0.5 W for supporting a broad range of interface standards, including DDR3, LPDDR3, XGMII and 7:1 LVDS, PCI Express, Ethernet (XAUI, GbE, SGMII) and CPRI.
The ECP5 FPGA family is supported with the Lattice Diamond® Software Tool. Devices are available immediately with production-qualification scheduled for August 2014. For more details, visit www.latticesemi.com/ecp5.