Altera Extends Life of NAND Flash Storage

July 2, 2015 | 10:09
Altera Extends Life of NAND Flash Storage
Altera Extends Life of NAND Flash Storage
The growing complexity of flash memory management algorithms has made controller designs complex and has impacted the performance and the diversity of NAND devices that a single controller can support. As the complexity of the controller design increases, there comes a point where hardware acceleration is necessary. We see this trend for partial FTL (Flash Translation Layer) layers, addressing and wear leveling, and command queuing.

At the same time, algorithms and flash device characteristics constantly change through the life of the controller. But data center managers expect the controller to constantly make design tradeoffs in order to improve in-system performance. These changes are also impacted by the traffic patterns of the application. The challenge is to provide hardware-accelerated algorithms that can change frequently in the field.

You may download the Solution Sheet below.
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Solution sheet: Advanced solid state memory controller
Altera announces a new FPGA-based storage reference design that doubles the life of NAND flash and boosts NAND utilization by implementing hardware off-load functionalities and faster effortless qualification updates.
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