On April 15, 2026, Elektor is hosting an online conference on the use of the RISC-V standard instruction set architecture (ISA). Thanks to its open, modular, and highly customizable approach, this architecture is becoming increasingly important in embedded systems and microcontrollers. The organizers are now inviting RISC-V experts to apply for the conference with compelling presentation proposals. The call for presentations is open until January 16.

The event “RISC-V – Open Architecture for Embedded, AI, and Automotive” is aimed at embedded systems engineers, hardware design engineers, firmware and software developers, automotive and mobility engineers, semiconductor industry professionals, scientific researchers, and students. The conference offers expertise, trends, and practical experience report for those target groups.

Call for Presentations: What Are We Looking for?

We are looking for presentations tailored to the target audience that cover topics such as the following:
 
  • RISC-V ISA and extensions: Overview of basic ISA (RV32I, RV64I) and optional extensions (M, A, F, vector, matrix, and security extensions)
  • User-defined instructions and domain-specific architectures (DSA): How companies can develop their own instruction sets for automotive, AI, or IoT
  • Trends in modular designs and their impact on performance and scalability
  • Open-source chip design and European semiconductor strategy: Role of RISC-V in initiatives such as Chips JU and the EU Chips Act
  • Firmware development for RISC-V: Use of C/C++ and Rust, debugging, virtual prototyping, and open-source RTOS (e.g., Zephyr, RT-Thread)
  • Software porting and optimization: strategies for migrating from ARM/x86 to RISC-V, including compiler intrinsics and memory models
  • Cybersecurity and security for automotive and IoT: hardware security features (e.g., CHERI extensions), secure boot, and functional safety according to ISO 26262
  • Software-defined vehicle and E/E architectures: Use of RISC-V in zonal and centralized vehicle architectures
  • Cyber Resilience Act and SBOM: Regulatory requirements and best practices for compliance
  • ADAS and autonomous systems: RISC-V-based solutions for real-time and safety-critical applications
  • Matrix and vector extensions for AI: Acceleration of neural networks and ML workloads on RISC-V
  • Open educational resources and FPGA prototyping: Practical approaches for teaching and research
  • The importance of open standards for Europe and global supply chains
  • Business cases and licensing models: How RISC-V is changing the cost structure and speed of innovation

The planned presentation length is 45 minutes. Accepted submissions will be followed by a 15-minute Q&A session. The final program is expected to be available in early February. Tickets for the online conference will then be available for purchase.