Beta LAYOUT - Multi-dimensional circuit carriers using additive manufacturing
At the beginning of 2016, many people were writing about the end of Moore's Law, anticipating that the performance of computer chips would no longer be doubling every two years. The reason for this is that the structures on the processors themselves are already within a few nanometers of what is possible. Further reductions are almost impossible from a technical point of view. In order to continue improving performance, manufacturers are working on the architecture, which stacks multiple structural layers on top of one another. A similar approach has already been established within the field of circuit carriers. The German firm of Beta LAYOUT GmbH has successfully harnessed EOS technology to manufacture and test the prototypes for these innovative carriers.