Elektor Team

Massive microprocessor array aims to simulate human brain

December 10, 2013 | 14:37
Massive microprocessor array aims to simulate human brain
Massive microprocessor array aims to simulate human brain

Up to a million ARM processor cores will be linked together to simulate the workings of the human brain in a UK research project. The chips, designed at Manchester University and manufactured in Taiwan, form the building blocks for a massively parallel computer called SpiNNaker (Spiking Neural Network architecture). Although the chips are based on a relatively old ARM instruction set architecture, the first samples were delivered to the university only last month and have subsequently passed functionality tests.

SpiNNaker is a joint project of the universities of Manchester, Southampton, Cambridge and Sheffield and is funded by a £5 million government grant. Professor Steve Furber of the University of Manchester has been studying brain function and architecture for several years, but is also well known as one of the co-designers of the Acorn RISC machine, a microprocessor that is the forerunner of today's ARM processor cores.

There are around 100 billion neurons with 1,000 trillion connections in the human brain. Even a machine with one million of the specialized ARM processor cores developed at Manchester would only allow modelling of approximately 1% of the human brain, the researchers said. In the SpiNNaker machine, neurons will be modelled as packets of descriptive data, and data channels will replace the nerve axons and electrical ‘spikes’ that provide communication between neurons. The contents of the data packets will be processed by virtual neurons running on the ARM microprocessors. The architecture and the use of packetised digital data allow SpiNNaker to transmit virtual spikes as quickly as the brain, with many fewer physical connections.

Although an initial test chip was designed by Professor Furber's team in 2009, the latest implementation has 18 ARM processors one each silicon die, which is packaged with a memory die and has a power budget of around one watt. The chip is being manufactured by UMC (Hsinchu, Taiwan) in 130-nm CMOS. It contains approximately million transistors, although most them are located in 55 32-kbyte SRAM blocks distributed over the die. The accompanying memory die is a 1-Gbit DDR SDRAM that operates at up to 166-MHz.


Image: Manchaster University

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