The Belgian research center for nanotechnology Imec and Cadence Design Systems have announced they are working on a tape-out of what will be the world's first 64-bit processor chip built using 3 nm technology.

At this structure width there are only around 12 silicon atoms next to each other, which is truly mind-boggling. The tape-out project was realized using Cadence software and Extreme Ultraviolet (EUV) and 193 immersion lithography-orientated design rules.
3-nm MCU tape-out. Source: Imec.

The illustrated test chip tape-out is a 64-bit MCU based on a standard cell library, with routing pitch reduced to 21 nm. Chips using 3 nm technology are targeted for production in 2023, the interconnections will require special care. The present implementation is particularly suitable for examining the electrical and physical parameters of such chips. This follows on from the implementation of 5 nm technology which Imec demonstrated in 2015 and gets closer to the physical barrier that will, one day, end the progression of Moore’s Law. This new 3 nm structure could mean a good 10-fold increase in packing density compared to the 10 nm technology, which Intel launched this year.