Digital audio stereo 2-way-crossover network with input select and volume control
This electronic circuit shows a digital audio stereo 2-way-crossover network and was designed for operating an active 2-way loudspeaker system. The lowpass audio signal values are calculated with an FIR filter, than the high pass signal is calculated through simple subtraction from the unfiltered audio signal.
Fullrange = Highpass + Lowpass or Highpass = Fullrange - Lowpass
This method has two advantages, the sum of high- and lowpass output is always identical with the fullrange input signal (ideal frequency separator) as well as the needed smaller calculating power. Digital signal controllers from Microchip, able to run with 70 MIPS, take over the task of audio signal filter value calculation. The controllers work with 16 bit audio data word length, an FIR filter length of 512 coefficients of 32 bit accuracy and sampling frequencies of 44.1 and 48 kHz.
The block diagram shows a simplified schematic diagram. One (of max. four) input SPDIF-signals is selected and converted to digital audio DSP format A. Over a bus system the audio data words are fed into the dsPIC33EP512GP806, the upper one works on the left channel, the lower one on the right channel audio data. The calculated high and low pass filter values are moved to the stereo DAC WM8252 one sample clock later. After converting to analog audio voltages the signals are fed to the volume control IC PGA2311 for level setting. At last the audio signals are buffered with operational amplifiers and could now drive power amplifiers directly, also with longer cables.
For parameterizing of all used digital IC, control of display, source selecting and volume setting a PIC18F2423 is used. A display shows the selected input source and the recognized sampling frequency. With a rotary encoder the input source is selected. After pushing the button of the rotary encoder the level of the lowpass outputs could be attenuated or amplified to compensate for different efficiency of the loudspeakers or different amplification of the power amps. Volume setting is realized through position detection of a potentiometer with the embedded ADC of the PIC.
To get the same filter response for 44.1 or 48 kHz audio data, the FIR-filters use two different sets of coefficients. Depending on the (recognized) sampling frequency the coefficients were switched in the digital signal controllers. If there is no digital input signal or the sampling frequency is to high the analog output will become 0V. Digital audio signals with data word length above 16 bit are automatically reduced to a data word length of 16 bit.
Not shown in the block diagram: a +-5V-power supply is necessary for working, the +5V-path must be able to provide more current, because the display and the complete digital part of the circuit is supplied from here (the hardware needs +240mA/-100mA). The power supply should be of low noise (no SMPS!) because the analog part ot the circuit is supplied directly from the +-5V-supply.
The supplement represents revision one of this project. Two relays in the output lines were added, to avoid a pop in the loudspeakers when the power amplifiers are already running and one switch on the digital separator. The supply currents for the relays (~ 70mA) come from the -5V-supply to get better balance of currents in the power supply.
The supplement contains the gerber files for the pcb (100x160mm² 2-layer), schematic, partlist and placeplan. For programming of dsPIC33EP-types a programming device like Pickit3 or ICD3 is necessary, older devices like ICD2 don't support these types! The parts are easy to solder, one small tip and one tip with solder reservoir are enough for SMD, even with fine pitch housing.
MPLAB 8.92 project file SepDig_Control_V2 contains the firmware of the µC PIC18F2423 (update)
I currently use the separator digital with a mono subwoofer and fullrange speakers, that's because the display shows "Sublevel" . Suit the lines concerning display text for your own use, also the names of the input sources.
Please pay attention to one issue: SPDIF-receiver WM8805 has only one flag for 44.1kHz and 48kHz sampling frequency. To differ between these two frequencies the indicated frequency read from the SPDIF-input stream of the source device has to be taken into account. If the source device has no correct entry here, the wrong sampling frequency is detected from separator digital. If you are unsure, please check the sampling frequency with an oscilloscope and then use a fixed assignment between input source and sampling frequency, as shown in the firmware. My digital radio NOXON resamples everything to the output sampling frequency of 48kHz but shows 44.1 kHz sampling frequency in the SPDIF-data stream.
A CD player should always show 44.1 kHz!
MPLAB 8.92 project file SepDig_Filter contains firmware for dsPIC33EP512GP806. There is only one file for both DSC IC3+4, the slight different functions were selected through reading of hardwired input pins.
Before subtracting the lowpass value from the fullrange input signal the calculated value must be divided by the formatting factor. The formatting factor was a power of two, shift the result right with the exponent is the same as dividing by the formatting factor, but even more faster.
When doing subtraction with two 16 bit values the result could be a 17bit value, for instance -32766 - 9 = -32775. This happens during filtering especially when the input signal is near maximum or minimum signal level. There is an overflow with wrap around. To avoid this the highpass value is calculated as signed 32 bit value, following that the value is shifted 15 bit left and send to the DAC as a 32 bit value, so the effective resolution is 17 bit now!
The lowpass signal is also converted to a signed 32 bit value, but here the effective resolution remains at 16 bit.
Firmware was updated to correct some errors in comments and one error in calculation of the highpass values!
A very useful software tool (and also freeware) to get coefficients for an FIR filter is "rePhase". The coefficient sets of rePhase are prepared for using them within the code of the digital signal controllers. The floating point values are formed to a signed 32 bit fixed point value through multiplying them with a formatting factor (a power of two). Then the coefficients are split into two 16 bit values, one upper and one lower part. Now the fast (single cycle!) MAC with dual data fetch instruction can be used in the firmware to calculate the audio data in real time.
The number of 512 coefficients allows filter orders of 2 above ~160 Hz, filter orders of 4 above ~500 Hz and filter orders of 8 above ~1,2 kHz.
Coefficients for lowpass FIR-filters without phase distortion should be symmetrical to the middle coefficient (for an odd number of filter taps it is the largest value) and the sum of all coefficients should be 1. When generating filter coefficients with rePhase use only rectangular windowing, because all other windowing functions create FIR-filters with phase distortion!!! The cut-off frequency in the rePhase window is at -6dB (not -3dB!), that is also the point, where the amplitude responses of highpass and lowpass of a crossover network without phase distortion are overlap.
Please correct a small error in rePhase output files: the file is not complete, two coefficients are missing for symmetry. Please add first and second value to the end of the list, then you get 513 symmetrical coefficients, that's the reason for the implemented header-files and the algorithm with 513 coefficients, although your choice in rePhase was 511 taps!
A spreadsheet helps to convert floating point values from rePhase to 16 bit values for the filter firmware. Just copy the values from the rephase txt-file fo the first column of the spreadsheet and choose a suitable formatting factor so that the coefficient in the middle is as close as possible to the maximum value of a 32 bit signed integer value. Please change also the filter firmware if the formatting factor is different from 2^38 (see comment in sourcecode). The last two columns then have to be copied to the coefficients header files. The attached zip-file contains the original rePhase-output, the spreadsheet with this coefficients, and the firmware-header for the 44.1kHz coefficient filter set.
The spreadsheet uses comma as decimal separator, in countries with point as decimal separator it won't work until comma is replaced with point!
The creator of rePhase modified his software to get symmetrical coefficients in the output files. Download rePhase 0.9.9 from >sourceforge.net/projects/rephase/. You can now also use other windowing functions because of the improved impulse symmetry. Just choose 513 taps and copy the 513 values from the txt-file to the spreadsheet.
The attenuation shown in the frequency response window of rePhase represents calculation with 32 bit-float coefficients when 32bit float output format is selected. This format has the best performance, if 16/24/32 bit integer is selected, the amplitude response changes: the higher the resolution of the coefficients the higher is the attenuation in stopband area. But there is no big difference between 32bit float and 32bit integer.
I've added a picture of the measured amplitude response of the digital separator, the measuring system is a soundcard with a 24bit/48kHz ADC and a SNR of 100dB. The amplitude plot of high- and lowpass looks unsymmetrically, but consider the sum of high- and lowpass is always matching the original fullrange data word. It is well suited: the small fullrange-speakers are relieved from high amplitude in the deep bass region and the big mono subwoofer is emitting only low frequent parts of the music and could therefore not be located. The curves met at 160Hz/-6dB!
The SNR of the circuit is around 93dB, the performance is not fulfilling a 16bit-DAC SNR of >96dB. Please remember: because of the extra headroom necessary for the highpass a range of 6dB SNR is lost (with a pure sine signal the maximum output signal is only half the voltage possible). Perhaps it makes sense to replace the DAC with a better one, but I'm not sure if I can hear a difference. A little crosstalk above 10kHz in the lowpass amplitude response is also visible, I will check if this happens in the relay or on pcb, I don't have it on my first pcb-version without relays.
For IC3+IC4 you can also use dsPIC33EP512MC806 instead of ~GP806, just change to the appropiate header-file and select the right device name in MPLAB, then recompile the project before programming the µCs.
Firmware SepDig_Control_V2 was updated: last used source will be set properly now during start up of the device and left limit stop of volume pot is now mute position!
It is possible to use this crossover technic also for a 3- or 4 way crossover. It is feasible to realize a stereo crossover with two boards of separator digital, because one board is able to give out four audio signals (one board is a mono crossover now). I think for building up an active 3- or 4-way speaker system it is necessary to check the amplitude response of the complete system in an anechoic chamber to get a flat response.
For integrating the crossover with the power amps in the loudspeaker housing an additional hardware board is necessary to transmit two SPDIF-signals with the volume information (and also setting of presets) to the left and right channel loudspeaker. The volume and preset information could be included in the user data space of the SPDIF-signal. Display, encoder and volume pot are connected to this new board. The digital separator board will work without the user interface and one fixed input source only for the left (or right) audio channel.