Cinque, the RISCy Arduino

July 3, 2017 | 11:48
Cinque, the RISCy Arduino. Image courtesy of LinuxGizmodos
Cinque, the RISCy Arduino. Image courtesy of LinuxGizmodos
Open-source hardware is meeting open-source instruction set architecture with SiFive announcing their Arduino Cinque — an Arduino development board employing the RISC-V ISA (Instruction Set Architecture).

After the $59 HiFive1 from late 2016, Cinque is the second RISC-V based development board released by SiFive.

Just a few prototypes of the Arduino Cinque were spotted at Maker Faire Bay Area last May. The board is thought to be hosted on SiFive’s Freedom E310 customizable SoC, which is derivate of the E31 CPU Coreplex with its 32-bit RV32IMAC Core. The Freedom E310 claims to be the fastest microcontroller on the market, capable of running at 320 MHz.

The Arduino Cinque will also have built-in Wi-Fi and Bluetooth capabilities with the inclusion of an efficient, low-power Espressif ESP32 Wi-Fi/Bluetooth hybrid chip.

At speed now... the tentative specs of Cinque.
Freedom E310: E310 CPU Coreplex (32-bit RV32IMAC core); 320 MHz operating speed; 16 KB L1 Instruction Cache; 16KB Data SRAM Scratchpad; hardware multiply/divide; debugging module; one-time programmable non-volatile memory (OTP); on-chip oscillators and PLLS; UART, QSPI, PWM, and timer peripherals; low-power standby mode; RV32IMAC specifications; RV32I Base Integer Instruction Set, Version 2.0; “M” Standard Extension for Integer Multiplication and Division, Version 2.0; “A” Standard Extension for Atomic Instructions, Version 2.0; “C” Standard Extension for Compressed Instructions, Version 1.9; RISC-V Privileged ISA Specification, Version 1.9.1; RISC-V External Debug Support, Version 0.11.

The RISC-V Foundation has been actively working to spread the idea and benefits of the open-source ISA, regularly hosting workshops, participating in conferences, and collaborating with academia and industry. The Foundation has also been working with researchers from Princeton University which identified flaws with the ISA design. The problem occurred in high-performance applications of RISC-V in which memory-ordering rules were being violated. The group presented their findings this past April at the 22nd ACM International Conference on Architectural Support for Programming Languages and Operating Systems.
 

About Jan Buiting

Jan Buiting (1958) has been active in electronics and ways of expressing it since the age of 15. Attempts at educating Jan formally have so far yielded an F-class radio amateur license, an MA degree in English, a Tek Guru award, and various certificates in ele... >>

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