Low Phase-Jitter clock chip

October 20, 2015 | 01:45
There are currently three variants available
There are currently three variants available
New from Integrated Device Technology, Inc. is their highly stable VersaClock 6 range of programmable clock generators. With RMS phase jitter of less than 500 femtoseconds (fsec) they deliver flexible, low-power timing for demanding high-performance applications.

The 500 fsec RMS jitter is achieved over the 12 kHz to 20 MHz integration range, and conforms to the stringent jitter and phase noise requirements of applications and standards such as 10G Ethernet, enterprise storage SAS and SATA, PCI Express Gen 1/2/3, XAUI, SRIO, stringent PHY reference clocks and the newest generations of high-end FPGAs. The clock generator draws 30 mA which helps reduce system thermal loading and operating power expenses.

The VersaClock 6 programmable clock generator offers universal output pairs that are independently configurable as LVDS, LVPECL, HCSL, or dual LVCMOS and can generate any output frequency from 1 MHz to 350 MHz on each output pair independently.

The new devices are the:

• 5P49V6901 with four outputs of any frequency
• 5P49V6913 with two outputs of any frequency
• 5P49V6914 with three outputs of any frequency

The 4 mm x 4 mm 24-VFQFPN package is footprint compatible with VersaClock 5 devices, enabling performance scalability with minimal design change. The VersaClock 6 family devices are available now with the 1K price of $5.20 for the 5P49V6901, $4 for the 5P49V6914 and $3.20 for the 5P49V6913.
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