New RISC-V Startup from Intel Architects
on
AheadComputing's launch comes shortly before Intel's announcement of a substantial workforce reduction, with plans to lay off approximately 15% of its global employees, totaling around 15,000 positions, Clarke reports.
Leadership Team
The leadership team at AheadComputing boasts a combined 80 years of microprocessor design experience:- Debbie Marr, CEO, formerly an Intel Fellow and chief architect at AADG, brings over 33 years of experience at Intel.
- Jonathan Pearce, a microprocessor architect with a 22-year tenure at Intel, held the role of Principal Engineer and CPU Architect.
- Srikanth Srinivasan, an architect who led both frontend and backend CPU teams at AADG.
- Mark Dechene, another seasoned microprocessor architect, served as a Principal Engineer at Intel, overseeing the memory execution architecture team during his 16 years with the company.
More on RISC-V
Interested in more architecture-related content? Refer to these Elektor resources:- What Is RISC-V?
- RISC-V Assembly Language Programming
- Getting Started with the ESP32-C3 RISC-V MCU
- Build Your Own RISC-V Controller
Editor's note: Our colleague Peter Clarke first reported this news in EENews Europe, a publication in the Elektor network.

Discussion (0 comments)