[Partner Content] Xilinx SmartLynq+ Module is intended for high-speed debug and trace, primarily targeting designs using the Versal™ platform.
High-speed debug and trace, primarily targeting designs using the Versal™ platform
Xilinx SmartLynq+ Module is intended for high-speed debug and trace, primarily targeting designs using the Versal™ platform. The SmartLynq+ Module delivers up to 28X faster configuration time via a high-speed debug port (HSDP). The SmartLynq+ Module has advanced configuration throughput performance to accelerate the development cycle. The Module supports both serial and parallel trace with up to 14GB of trace memory to capture a design execution history.
The Xilinx SmartLynq+ Module
The Xilinx SmartLynq+ Module is compatible with Versal ACAP evaluation boards. Users have complete visibility to the Versal™ architecture, including AI Engines, programmable network on chip (NoC), DDR memory controller, and 100G multirate Ethernet cores.
Furthermore, smart filtering with a software customizable built-in debugger facilitates remote access and sharing. The SmartLynq+ Module is an ideal debug and trace platform, enabling fast configuration, extensive trace capture, high visibility, and flexibility.
Features
28X faster download speed vs. SmartLynq Data Cable
Iterations reduced from minutes to seconds for the shorter debug cycle
100X faster egress data capture vs. JTAG
Large trace memory (up to 14GB)
In-depth debug and trace for Versal architecture, including AI Engines, programmable NoC, DDR memory controller, and 100G multirate Ethernet cores
Continuous debug and trace visibility during boot
Cohesive and time-correlated debug of all subsystems
Daisy-chain mode to debug multiple devices on a single board
Smart filtering with software programmable built-in debugger for remote access and sharing
A range of host and target connectivity options, including Ethernet, USB 3.0, HSDP (USB Type-C), GPIO, JTAG, and Mictor
Discussion (0 comments)