Expanded dual- and single-core dsPIC® Digital Signal Controller (DSC) family builds larger, more robust applications

March 13, 2019 | 12:00
Expanded dual- and single-core dsPIC® Digital Signal Controller (DSC) family builds larger, more robust applications
Expanded dual- and single-core dsPIC® Digital Signal Controller (DSC) family builds larger, more robust applications
Microchip announces new dual- and single-core dsPIC33C Digital Signal Controllers (DSCs) with more options to meet changing application requirements across memory, temperature and functional safety. These options will help system developers to design high-end embedded control applications which need flexible options to provide scalability as projects increase in complexity.
 
Key Facts:
  • More memory and functional safety features for automotive and wireless charging
  • Offers scalability for projects to increase in complexity with pin-compatibility to dsPIC33CH/K
  • dsPIC33CH512 expands to 512 KB Flash memory and triples programme RAM to 72 KB
  • Cost-optimised dsPIC33CK64 offers 64 KB Flash in a footprint down to 4 mm x 4 mm

The new dsPIC33CH512MP508 dual-core DSC enables support for applications with larger programme memory requirements. The dsPIC33CK64MP105 single-core DSC adds a cost-optimised version for applications that require smaller memory and footprint. Developers can easily scale across product lines using the new devices, which are pin-to-pin compatible within the dsPIC33CH and dsPIC33CK families.

The dsPIC33CH512MP508 (MP5) family expands the recently introduced dsPIC33CH with Flash memory growing from 128 KB to 512 KB and triples the programme RAM from 24 KB to 72 KB. This enables support for larger applications with multiple software stacks or larger programme memory, such as automotive and wireless charging applications. More memory is needed to accommodate AUTOSAR software, MCAL drivers and CAN FD peripherals in automotive applications. Implementing wireless charging in automotive applications requires additional software stacks for the Qi protocol and Near-Field Communication (NFC), driving the need for even more programme memory. Using Live Update capability for real-time firmware updates is essential for high-availability systems but also doubles the overall memory requirement. In the dual-core devices, one core can function as a master while the other is designed as a slave. The slave core is useful for executing dedicated, time-critical control code while the master core is busy running the user interface, system monitoring and communications functions. For example, having two cores facilitates partitioning of the software stacks for parallel execution of the Qi protocol and other functions such as NFC to optimise performance in automotive wireless charging applications.
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